Quaternary Logic Look up Table for Cmos Circuits

Interconnections are increasingly one of the dominant contributors to delay, area and energy consumption in CMOS digital circuits now a days. Multiple Valued Logic (MVL) can decrease the average power required for level transitions and also the number of required interconnections are reduced. So the impact of interconnections on overall energy consumption is reduced. In this paper, a quaternary Look Up Table (LUT) structure is designed to replace or complement binary LUTs in Field Programmable Gate Array (FPGA)s. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltage mode structures. A half adder prototype based on the designed LUT, fabricated in a standard 180-nm CMOS technology, able to work at 100 MHz is developed. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design. Index Terms Field-programmable gate array (FPGA), Look Up Table (LUT), Multiple-Valued Logic (MVL), Quaternary Logic, Standard CMOS technology.